Conventionally, an emitter follower circuit is used as an input circuit for inputting a signal or an output circuit for outputting a signal.
In a bipolar-complementaly metal oxide semiconductor (Bipolar-CMOS) circuit constructed by combining a bipolar circuit and a CMOS circuit, a MOS transistor included in a current source is cut off when the emitter follower circuit is set to the inactive state. Thereby, it becomes possible to prevent current from passing through the bipolar circuit and reduce power consumed therein.
FIG. 1 illustrates a level converter, which includes a conventional emitter follower circuit. Referring to FIG. 1, a differential circuit is made up of transistors Q1 and Q2. The transistor Q1 is supplied with a voltage signal through a terminal 10, and the transistor Q2 is supplied with a reference voltage V.sub.REF through a terminal 11.
Two output signals derived from the differential circuit pass through emitter follower circuits 12 and 13 including transistors Q3 and Q4, respectively, and are supplied to a flip-flop 14, which includes MOS transistors P1, P2, N1 and N2. An output signal derived from the flip-flop 14 passes through an inverter 15 including MOS transistors P3 and N3, and is output through a terminal 16. The flip-flop 14 has a function of converting the ECL (Emitter Coupled Logic) level of a supplied signal to the MOS level.
The emitter follower circuits 12 and 13 include transistors Q5 and Q6, respectively, which function as constant-current sources, each of which is supplied to a fixed voltage V.sub.R through a terminal 17. N-channel MOS transistors N4 and N5 are current source resistors, and conduct when a chip select signal CS applied through a terminal 18 is held at a high (H) level, so that emitter follower circuits 12 and 13 are held in the active state. The MOS transistors N4 and N5 are cut off when the chip select signal CL is switched to a low (L) level, so that the emitter follower circuits 12 and 13 are switched to the inactive state.
FIG. 2 illustrates a sense amplification circuit for a memory including a conventional emitter follower circuit. Referring to this figure, terminals 20a and 20b are connected to bit lines (not shown) which are paired. The voltages of the terminals 20a and 20b pass through emitter follower circuits 21 and 22 including transistors Q10 and Q11, respectively, and are then applied to a differential circuit made up of transistors Q12 and Q13. The collectors of the transistors Q12 and Q13 are coupled to corresponding current/voltage conversion circuits 25 and 26 through corresponding common lines 23 and 24, which are used in common with differential circuits associated with other bit lines. With the above-mentioned structure, current passing through the common line 23 becomes larger than that passing through the common line 24 when the level of the terminal 20a is higher than the level of the terminal 20b. At this time, the levels of the common lines 23 and 24 are held at almost identical levels.
A fixed voltage V.sub.CNO is applied, through a terminal 30, to the base of transistors Q14 and Q15, which are included in the current/voltage conversion circuits 25 and 26, respectively. Collector currents of the transistors Q14 and Q15 are converted to corresponding voltages by the MOS transistors N12 and N13, respectively, which function as resistors.
The output signals of the current/voltage conversion circuits 25 and 26 are supplied to a differential amplifier (not shown) of the next stage through terminals 27a and 27b, respectively.
The N-channel MOS transistors N10 and N11 included in the emitter follower circuits 21 and 22 are current source resistors. The MOS transistors N10 and N11 conduct when a bit select signal BS supplied from a terminal 28 through an inverter is held at L level, whereby the emitter follower circuits 21 and 22 are held in the active state. On the other hand, the MOS transistors N10 and N11 are cut off when the bit select signal BS is held at H level, so that the emitter follower circuits 21 and 22 are held in the inactive state.
Turning to FIG. 1, when the emitter follower circuits 12 and 13 are switched to the inactive state, the potential of the emitter of each of the transistors Q3 and Q4 becomes unstable. Therefore, the flip-flop 14 becomes unstable, and the input signal of the inverter 15 is unnecessarily inverted. It is noted that the circuit of FIG. 1 is wasteful of current when the MOS transistors P1, P2, N1 and N2 included in the flip-flop 14 and the inverter 15 are inverted. The above leads to an increase of consumption power.
In the circuit of FIG. 2, the potential of emitter of each of the transistors Q10 and Q11 becomes unstable, when the emitter follower circuits 21 and 22 are switched to the inactive state. The emitter potentials of the transistors Q10 and Q11 decrease to the ground level (Vcc) as time goes. Therefore, it takes long for the emitter potential of each of the transistors Q10 and Q11 to become equal to the predetermined potential when the emitter follower circuits 21 and 22 is set to the active state again. The above prevents the sense amplifier from operating at high speeds.